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high temperature, 16 - bit, 600 ksps pulsar ? adc data sheet AD7981 features extreme high temperature operation specified temperature range: ?55c to +175c high p erformance 16- bit resolution with no missing codes 600 ksps throughput with no latency/pipeline delay snr: 91 db typ ical at 1 khz input frequency thd: ? 10 2 db t yp ical at 1 khz input frequency inl: 2.0 lsb max imum , dnl: 0.9 lsb max imum low power dissipation 2.25 mw typical at 600 ksps (vdd only) 4.65 mw typical at 600 ksps ( t otal) 70 w typical at 10 ksps small f ootprint 10- lead , 3 mm 5 mm , mono metallic wir e bonding msop pseudo differential analog input range 0 v to v ref with v ref between 2.4 v and 5.1 v easy to use single - supply 2.5 v operation with 1.8 v/2.5 v/3 v/5 v logic i nterface spi - /qspi - /microwire - /dsp - compatible digital interface daisy - chain multi ple adcs and busy indicator applications downhole drilling and instrumentation avionics heavy i ndustrial high temperature environments typical application circuit AD7981 ref gnd vdd in+ in? vio sdi sck sdo cnv 1.8v t o 5.0v 3- or 4-wire inter f ace (spi, dais y chain, cs) 2.5v to 5.0v 2.5v 0v t o v ref 12479-001 figure 1. general description the AD7981 1 is a 16 - bit, successive approximation, analog - to - digital converter (adc) designed for high temperature operation . the AD7981 is ca pable of sample rates up to 600 ksps while maintaining low power consumption from a single power supply, vdd. it is a fast throughput, high accuracy , hig h temperature , s uccessive approximation register (sar) adc and packaged in a small form factor with a versatile serial port interface (spi). on the cnv rising edge, the AD7981 samples an analog input, in+, between 0 v and ref with respect to a ground sense , in?. the reference voltage, ref, is applied externally and can be set independent of the supply voltage, vdd. the device power scal es linearly with throughput. the spi - compatible serial interface also features the ability, using the sdi input, to daisy - chain several adcs on a single, 3 - wire bus and provides an optional busy indicator. it is compatible with 1.8 v, 2.5 v, 3 v, or 5 v l ogic, using the separate supply vio. for space constrained applications, the AD7981 is available in a 10- lead mini small outline package (msop) with operation specified from ?55c to +175c. this package is designed for robustness at extre me temperatures, including mono metallic wire bonding , and is qualified for up to 1000 hours of operation at the maximum temperature rating. the AD7981 is a member of a growing series of high temperature qualified products offered by analog devices, inc. for a complete selection of avail able high temperature products, see the high temperature product list and qualification data available at www.analog.com/hightemp . 1 protected by u.s. patent 6,703,961. rev. 0 document feedback information furnished by anal og devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change wi thout notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9 106, u.s.a. tel: 781.329.4700 ? 2014 analog devices, inc. all rights reserved. technical support www.ana log.com
AD7981 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical application circuit ............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 t erminology .................................................................................... 12 theory of operation ...................................................................... 13 circuit information .................................................................... 13 conv erter operation .................................................................. 13 typical connection diagram .................................................... 14 analog input ............................................................................... 15 driver amplifier choice ........................................................... 15 voltage reference input ............................................................ 16 power supply ............................................................................... 16 digital interface .......................................................................... 16 cs mode, 3 - wire without busy indicator ............................. 17 cs mode, 3 - w ire with busy indicator .................................... 18 cs mode, 4 - wire without busy indicator ............................. 19 cs mode, 4 - wi re with busy indicator .................................... 20 chain mode without busy indicator ...................................... 21 chain mode with busy indicator ............................................. 22 applications information .............................................................. 23 printed circuit board (pcb) layout ....................................... 24 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 25 revision history 10 /14 revision 0 : initial version rev. 0 | page 2 of 25
data sheet AD7981 specifications vdd = 2.5 v, vio = 2.3 v to 5.5 v, v ref = 5 v, t a = ? 55 c to +1 7 5c, unless otherwise noted. table 1 . parameter test conditions/comments min typ max unit resolution 16 bits analog input voltage range in+ ? in? 0 v ref v absolute input voltage in+ ?0.1 v ref + 0.1 v in? ?0.1 +0.1 v analog input common - mode rejection ratio (cmrr) f in = 100 khz 60 db leakage current at 25c acquisition phase 1 na input impedance see the analog input section accuracy no missing codes 16 bits differential nonlinearity v ref = 5 v ? 0.9 0.4 + 0.9 lsb 1 v ref = 2.5 v 0. 5 lsb 1 integral nonlinearity v ref = 5 v ?2 .0 0.7 +2.0 lsb 1 v ref = 2.5 v 0 .6 lsb 1 transition noise v ref = 5 v 0.75 lsb 1 v ref = 2.5 v 1.2 lsb 1 gain erro r 2 t min to t max 2 lsb 1 gain error temperature drift 0.35 ppm/c zero error 2 t min to t max ? 1 0.08 + 1 mv zero temperature drift 0. 45 ppm/c power supply sensitivity vdd = 2.5 v 5% 0.1 lsb 1 throughput conversion rate 0 600 k sps transient response full - scale step 290 ns ac accuracy 3 dynam ic range v ref = 5 v 9 2 db v ref = 2.5 v 8 7 db oversampled dynamic range 4 osr = 256 110 db signal -to - noise ratio (snr) f in = 1 khz, v ref = 5 v 89 91 db f in = 1 khz, v ref = 2.5 v 8 6 db spurious - free dynamic range (sfdr) f in = 1 khz 104 db total harmonic distortion (thd) f in = 1 khz ?10 2 db signal - to - noise - and - distortion (sinad) f in = 1 khz, v ref = 5 v 90.5 db f in = 1 khz, v ref = 2.5 v 85.5 db 1 lsb means least significant bit. with the 5 v input range, 1 lsb is 76.3 v. 2 see the terminology section. these specifications include full temperature range variation , but not the error contribution from the external reference. 3 all ac accuracy specifi cations in db are referred to an input full - scale range (fsr). tested with an inp ut signal at 0.5 db below full scale, unless otherwise specified. 4 the oversampled dynamic range is the ratio of the peak signal power to the noise power (for a small input) measured in th e adc output fft from dc up to f s /(2 osr), where f s is the adc sa mple rate and osr is the oversampling ratio. rev. 0 | page 3 of 25
AD7981 data sheet vdd = 2.5 v, vio = 2.3 v to 5.5 v, v ref = 5 v, t a = ? 55 c to +1 7 5c, unless otherwise noted. table 2 . par ameter test conditions/comments min typ max unit reference voltage range 2.4 5.1 v load current 600 ksps , v ref = 5 v 330 a sampling dynamics ?3 db input bandwidth 10 mhz aperture delay vdd = 2.5 v 2.0 ns digital inputs lo gic levels v il vio > 3 v C 0.3 0.3 vio v vio 3 v C 0.3 0.1 vio v v ih vio > 3 v 0.7 vio vio + 0.3 v vio 3 v 0.9 vio vio + 0.3 a i il ?1 +1 a i ih ?1 +1 a digital outputs data format serial 16 bits straight binary p ipeline delay conversion results available immediately after completed conversion v ol i sink = 500 a 0.4 v v oh i source = ?500 a vio ? 0.3 v power supplies vdd 2.375 2.5 2.625 v vio specified performance 2.3 5.5 v vio range 1.8 5.5 v standby current 1 , 2 vdd and vio = 2.5 v 0.35 a power dissipation vdd = 2.625 v, v ref = 5 v, vio = 3 v total 10 ksps 70 w 600 ksps 4.65 7.0 mw vdd only 600 ksps 2.25 mw ref only 600 ksps 1.5 mw vio only 600 ksps 0.9 mw energy pe r conversion 7.75 nj/sample temperature range specified performance 3 t min to t max ? 55 +1 7 5 c 1 with all digital inputs forced to vio or gnd as required. 2 during the acquisition phase. 3 q ualified for up to 1000 hours of operation at the maximum temperature rating. rev. 0 | page 4 of 25
data sheet AD7981 timing specification s t a = ? 55 c to +1 7 5c, vdd = 2.37 5 v to 2.6 25 v, vio = 3.3 v to 5.5 v, unless otherwise stated. see figure 2 and figure 3 for load condi tions. table 3 . parameter symbol min typ max unit conversion time: cnv rising edge to data available t conv 6 25 900 ns acquisition time t acq 290 ns time between conversions t cyc 1 667 ns cnv pulse width ( cs mode) t cnvh 10 ns sck period ( cs mode) t sck vio above 4.5 v 10.5 ns vio above 3 v 12 ns vio above 2.7 v 13 ns vio above 2.3 v 15 ns sck period (chain mode) t sck vio above 4.5 v 11.5 ns vio above 3 v 13 ns vio above 2.7 v 14 ns vio above 2.3 v 16 ns sck low time t sckl 4.5 ns sck high time t sckh 4.5 ns sck falling edge to data remains valid t hsdo 3 ns sck falling edge to data valid delay t dsdo vio above 4.5 v 9.5 ns vi o above 3 v 11 ns vio above 2.7 v 12 ns vio above 2.3 v 14 ns cnv or sdi low to sdo d15 msb valid ( cs mode) t en vio above 3 v 10 ns vio above 2.3 v 15 ns cnv or sdi high or last sck falling edge to sdo high i mpedance ( cs mode) t dis 20 ns sdi valid setup time from cnv rising edge t ssdicnv 5 ns sdi valid hold time from cnv rising edge ( cs mode) t hsdicnv 2 ns sdi valid hold time from cnv rising edge (chain mo de) t hsdicnv 0 ns sck valid setup time from cnv rising edge (chain mode) t ssckcnv 5 ns sck valid hold time from cnv rising edge (chain mode) t hsckcnv 5 ns sdi valid setup time from sck falling edge (chain mode) t ssdisck 2 ns sdi valid hold time from sck falling edge (chain mode) t hsdisck 3 ns sdi high to sdo high (chain mode with busy indicator) t dsdosdi 15 ns 500 a i o l 500 a i oh 1.4v t o sdo c l 20pf 12479-002 figure 2 . load circuit for digital interface timing x% vio 1 y% vio 1 v ih 2 v il 2 v il 2 v ih 2 t delay t delay 1 for vio 3.0v, x = 90 and y = 10; for vio > 3.0v, x = 70 and y = 30. 2 minimum v ih and maximum v il used. see digital inputs specifications in table 2. 12479-003 figure 3 . voltage le vels for timing rev. 0 | page 5 of 25
AD7981 data sheet absolute maximum rat ings table 4 . parameter rating analog inputs in+, in? to gnd 1 ?0.3 v to v ref + 0.3 v or 130 ma supply voltage ref, vio to gnd ?0.3 v to +6 v vdd to gnd ?0.3 v to +3 v vdd to vio +3 v to ?6 v digital inputs to gnd ?0.3 v to vio + 0.3 v digital outputs to gnd ?0.3 v to vio + 0.3 v storage tempe rature range ?65c to +150c junction temperature 17 6.4c thermal impedance (10 - lead msop) ja 200c/w jc 44c/w lead temperature vapor phase (60 sec) 215c infrared (15 sec) 220c esd ratings human body model 2 kv machine model 200 v field - induced charged device model 1.25 kv 1 see the analog input section. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating onl y; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliabi lity. esd caution rev. 0 | page 6 of 25
data sheet AD7981 pin configuration and function descriptions 12479-004 r ef 1 vdd 2 in+ 3 in? 4 gnd 5 vio 10 sdi 9 sck 8 sdo 7 cn v 6 ad 798 1 top view (not to scale) f igure 4 . pin configuration t able 5 . pin function descriptions pin no. mnemonic type 1 description 1 ref ai reference input vo ltage. the ref range is from 2.4 v to 5.1 v. it is referred to the gnd pin. decouple ref with a 10 f capacitor as close as possible to the pin. 2 vdd p power supply. 3 in+ ai analog input. this pin is referred to in?. the voltage range, for example, the difference between in+ and in?, is 0 v to v ref . 4 in? ai analog input ground sense. connect this pin to the analog ground plane or to a remote sense ground. 5 gnd p power supply ground. 6 cnv di conversion input. this input has multiple functions. on its leading edge, it initiates the conversions and selects the interface mode of the device : chain or cs mode. in cs mode, it enables the sdo pin when low. in chain mode, r ead the data when cnv is high. 7 sdo do serial data output. the conversion result is output on this pin. it is synchronized to sck. 8 sck di serial data clock input. when the device is selected, the conversion result is shifted out by this clock. 9 sdi di serial data input. this input provides multiple features. it selects the interface mode of the adc as follows : chain mode is selected if sdi is low during the cnv rising edge. in this mode, sdi is used as a data input to daisy - chain the conversion results of two or more adcs onto a single sdo line. the digital data level on sdi is output on sdo with a delay of 16 sck cycles. cs mode is selected if sdi is high during the cnv rising edge. in this mode, either sdi or cnv can enable the serial output signals when low . if sdi or cnv is low when the conversion is complete, the busy indicator feature is enabled. 10 vio p input/output interface digital power. nominally at the same supply as the host interface (1.8 v, 2.5 v, 3 v, or 5 v). 1 ai = analog input, di = digital input, do = digital output, and p = p ower . rev. 0 | page 7 of 25
AD7981 data sheet typical performance characteristics vdd = 2.5 v, v ref = 5.0 v, vio = 3.3 v, unless otherwise noted. 25c 175c ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1 6901 13801 20701 27601 34501 41401 48301 55201 62101 inl (lsb) code 12479-006 figure 5 . integral nonlinearity (inl) vs. code and temperature , v ref = 5.0 v ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1 6397 12793 19189 25585 31981 38377 44773 51169 57565 63961 inl (lsb) code 25c 175c 12479-007 figure 6 . integral nonlinearity (inl) vs. code and temperature , v ref = 2.5 v 0 ?180 0 500 frequency (khz) amplitude (db of full scale) ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 100 200 300 400 f s = 1 msps f in = 10khz snr = 91.3db thd = ?104.9db sfdr = 105.5db sinad = 90.8db 12479-038 figure 7. 10 khz fft, v ref = 5.0 v 1 6901 13801 20701 27601 34501 41401 48301 55201 62101 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 dnl (lsb) code 25c 175c 12479-008 figure 8 . differential nonlinearity (dnl) vs. code and temperature , v ref = 5.0 v ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 1 6557 13113 19669 26225 32781 39337 45893 52449 59005 dnl (lsb) code 25c 175c 12479-009 fi gure 9 . differential nonlinearity (dnl) vs. code and temperature , v ref = 2.5 v 0 ?180 0 500 frequency (khz) amplitude (db of full scale) ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 100 200 300 400 f s = 1 msps f in = 10khz snr = 86.4db thd = ?103.7db sfdr = 104.2db sinad = 86db 12479-058 figure 10 . 10 khz fft , v ref = 2.5 v rev. 0 | page 8 of 25
data sheet AD7981 180k 0 800c 800d 800e 800f 80098008 800b 800 a 8003 80058004 80078006 2 0 0 0 33 829 0 27 0 1201 code in hex counts 140k 160k 100k 120k 60k 20k 80k 40k 38751 168591 52710 12479-042 figure 11 . histogram of a dc input at the code center, v ref = 5.0 v 70k 0 7fff 8008 8001 8000 8003 8002 8005 8004 8007 8006 0 0 150 2 59691 5428 59404 3 93 code in hex counts 60k 50k 30k 10k 40k 20k 6295 12479-043 figure 12 . histogram of a dc input at the code transition, v ref = 5.0 v 1 1.00 1 1.25 1 1.50 1 1.75 12.00 12.25 12.50 12.75 13.00 13.25 13.50 13.75 14.00 14.25 14.50 14.75 15.00 15.25 15.50 15.75 16.00 80 82 84 86 88 90 92 94 96 98 100 2.00 2.50 3.00 3.50 4.00 4.50 5.00 5.50 sinad (db) enob (db) v ref (v) ?55c +175c +25c 12479- 1 14 sinad enob figure 13 . sinad and enob vs. reference voltage (v ref ) 60k 0 7f fa 8006 7ffc 7ffb 7ffe 7fff 7ffd 80018000 8003 8004 8005 8002 0 0 00 539 16 14 502 code in hex counts 50k 30k 10k 40k 20k 32417 52212 31340 7225 6807 12479-059 figure 14 . histogram of a dc input at the code center, v ref = 2.5 v 95 85 87 89 92 91 93 94 86 88 90 ?10 0 input level (db of full scale) snr (db) ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 12479-046 figure 15 . snr vs. input level 80 85 90 95 100 105 1 10 ?120 ?1 18 ?1 16 ?1 14 ?1 12 ?1 10 ?108 ?106 ?104 ?102 ?100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 thd (db) sfdr (db) v ref (v) ?55c +175c +25c 12479- 1 17 sfdr thd figure 16 . thd and sfdr vs. reference voltage (v ref ) rev. 0 | page 9 of 25
AD7981 data sheet 75 80 85 90 95 100 1k 10k 100k 1m sinad (db) input frequenc y (hz) ?55c +175c +25c 12479- 1 18 figure 17 . sinad vs. input frequency 80 82 84 86 88 90 92 94 96 98 100 ?60 ?40 ?20 0 20 40 60 80 100 120 140 160 180 200 snr (db) temper a ture (c) snr a t v ref = 5v snr a t v ref = 2.5v 12479- 1 19 fiure s teerature 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 2.375 2.425 2.475 2.525 2.575 2.625 oper a ting current (ma) vdd (v) 12479-120 i vdd i vio i ref fiure eratin urrents s u otae ?1 10 ?105 ?100 ?95 ?90 ?85 ?80 1k 10k 100k frequenc y (hz) 1m thd (db) ?55c +175c +25c 12479-121 figure 20 . thd vs. frequency ?109 ?108 ?107 ?106 ?105 ?104 ?103 ?102 ?101 ? 60 ? 10 40 90 140 190 thd (db) temper a ture (c) thd a t v ref = 5v thd a t v ref = 2.5v 12479-122 fiure t s te erature 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 ?55 ?30 ?5 20 45 70 95 120 145 170 oper a ting current (ma) temper a ture (c) i vdd i vio i ref 12479-123 fiure eratin urrents s teerature rev. 0 | page 10 of 25
data sheet AD7981 0 20 40 60 80 100 120 140 160 180 200 ?60 ?40 ?20 0 20 40 60 80 100 120 140 160 180 200 220 typica l power-down current (a) temper a ture (c) i vdd i vio i vdd + i vio 12479-124 figure 23 . power - down current vs. temperature rev. 0 | page 11 of 25
AD7981 data sheet terminology integral nonlinearity (inl) inl refers to the deviation of each indiv idual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the de viation is measured from the middle of each code to the true straight line (see figure 25). differential nonlinearity (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it i s often specified in terms of resolution for which no missing codes are guaranteed. zero error the first transition occur s at a level ? lsb above analog ground (38.1 v for the 0 v to 5 v range). the offset error is the deviation of the actual transition from that point. gain error the last transition (from 111 10 to 111 11) occur s for an analog voltage 1? lsb below the nominal full scale (4.999886 v for the 0 v to 5 v range). the gain error is the deviation of the actual level of the last transition f rom the ideal level after the offset is adjusted out. spurious - free dynamic range (sfdr) sfdr is the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measure ment of the resolution with a sine wave input. it is related to sinad by the following formula : enob = ( sinad db ? 1.76)/6.02 and is expressed in bits. noise - free code resolution noise - free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. it is calculated as noise - free code resolution = log 2 (2 n / peak - to - peak noise ) and is expressed in bits. effective resolution effective resolution is calculated as effective resolution = log 2 (2 n / rms input noise ) and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmon ic components to the rms value of a full - scale input signal and is expressed in db. dynamic range dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. it is measured with a signal a t ?60 dbfs to include all noise sources and dnl artifacts. the value for dynamic range is expressed in db. signal -to - noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the ny quist frequency, excluding harmonics and dc. the value for snr is expressed in db. signal -to - noise - and - distortion (sinad) ratio sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquis t frequency, including harmonics but excluding dc. the value for sinad is expressed in db. aperture delay aperture delay is the measure of the acquisition performance. it is the time between the rising edge of the cnv input and when the input signal is hel d for a conversion. transient response transient response is the time required for the adc to accurately acquire its input after a full - scale step function is applied. rev. 0 | page 12 of 25
data sheet AD7981 theory of operation 12479-011 com p switches contro l bus y output code cnv contro l logic sw+ lsb sw? lsb in+ ref gnd in? msb msb c c 4c 2c 16,384c 32,768c c c 4c 2c 16,384c 32,768c figure 24 . adc simplified schematic circuit information the AD7981 is a fast, low power, single - supply, precise 16 - bit adc that uses a successive approximation architecture. the AD7981 is capable of converting 60 0,000 samples per second ( 600 k sps) and powers down between conversions. when operating at 10 ksps, for example, it consumes 70 w typically, ideal for battery - powered applications. the AD7981 provides the user with on - chip track - and - hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications. the AD7981 can be interfaced to any 1.8 v to 5 v digital logic family. it is housed in a 10 - lead msop that combines space savings and allows flexible configurations. it is pin - for - pin compatible with the 18 - bit ad7982 . converter operation the AD7981 is a successi ve approximation adc based on a charge redistribution digital - to - analog converter ( dac ) . figure 24 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs. during the acquisition phase, terminals of the array t ied to the input of the comparator are connected to gnd via the sw+ and sw? switches . all independent switches are connected to the analog inputs. therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the in+ and in? inputs. when the acquisition phase is completed and the cnv input goes high, a conversion phase is initiated. when the conversion phase begins, sw+ and sw? are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the gnd input. therefore, the differential voltage between the inputs , in+ and in? , captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between gnd and ref, the comparator input varies by binary weighted voltage steps (v ref /2, v ref /4 v ref /65,536). the control logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. after the completion of this process, the device returns to the acquisition pha se , and the control logic generates the adc output code and a busy signal indicator. because the AD7981 has an on - board conversion clock, the serial clock, sck, is not required for the conversion process. rev. 0 | page 13 of 25
AD7981 data sheet transfer functions the ideal transfer characteristic for the AD7981 is shown in figure 25 and table 6 . 000 ... 000 000 ... 001 000 ... 010 11 1 ... 101 11 1 ... 1 10 11 1 ... 11 1 ?fsr ?fsr + 1lsb ?fsr + 0.5lsb +fsr ? 1 lsb +fsr ? 1.5 lsb analog input adc code (straight binary) 12479-012 figure 25 . adc ideal transfer function tale 6 . output codes and ideal input voltages analog input description v ref = 5 v digital output code fsr C 1 lsb 4.999924 v 0x ffff 1 midscale + 1 lsb 2.500076 v 0x 8001 midscale 2.5 v 0x 8000 midscale C 1 lsb 2.499924 v 0x 7fff C fsr + 1 lsb 76.3 v 0x 0001 C fsr 0 v 0x 0000 2 1 this is also the code for an overranged analog input (v in+ ? v in? above v ref ? v gnd ). 2 this is also the code for an underranged analog input (v in+ ? v in? bel ow v gnd ). typical connection d iagram figure 26 shows an example of the recommended connection diagram for the AD7981 when multiple supplies are available. AD7981 3- or 4-wire interface 5 2.5v 49.9 v+ v? 0v to v ref 1.8v to 5v 100nf 10f 2 100nf driver amplifier 3 reference buffer 100nf v+ 2.7nf 4 100nf ref in+ in? vdd vio sdi cnv sck sdo gnd ref 1 v+ v? 1 see the voltage reference input section for reference selection. 2 c ref is usually a 10f ceramic capacitor (x5r). 3 see the driver amplifier choice section. 4 optional filter. see the analog input section. 5 see the digital interface for the most convenient interface mode. 12479-013 figure 26 . typical application diagram with multiple supplies rev. 0 | page 14 of 25
data sheet AD7981 analog input figure 27 shows an equivalent circuit of the input structure of the AD7981 . the two diodes, d1 and d2, provide esd protection for the analog inputs, in+ and in?. ensure that the analog input signal never exceeds the supply rails by more than 0.3 v, because this causes these diodes to become forward - biased and to start conductin g current. a transient with a very short duration of 10 ms applied on the analog inputs, in+ and in ?, during latch - up testing shows that t hese diodes can then handle a forward - biased current of 130 ma maximum. for instance, these conditions may eventually occur when the supplies of the input buffer (u1) are different from vdd. in such a case (for example, an input buffer with a short circuit), the current limitation can be used to protect the device . ref r in c in in+ or in? gnd d2 c pin d1 12479-014 figure 27 . equivalent analog i nput circuit the analog input structure allows the sampling of the true differential signal between in+ and in?. by using these differential inputs, signals common to both inputs are rejected. during the acquisition phase, the impedance of the analog inputs (in+ and in?) can be modeled as a parallel combination of the c apacitor, c pin , and the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 400 ? and is a lumped component made up of some serial resistors and the on resistance of the switches. c in is typically 30 pf and is mainly the adc sampling capacitor. during the conversion phase, where the switches are opened, the input impedance is limited to c pin . r in and c in make a one - pole, low - pass filter that reduces undesirable aliasing effects and limits the noise . when the source impedance of the driving circuit is low, the AD7981 can be driven directly. large source impedances significantly affect the ac performance, especially thd. the dc performances ar e less sensitive to the input impedance. the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades as a function of the source impedance and the maximum input frequency. driver amplifier cho ice although the AD7981 is easy to drive, the driver amplifier must meet the following requirements: ? the noise generated by the driver amplifier must be kept as low as possible to preserve the snr and transition noise pe rformance of the AD7981 . the noise coming from the driver is filtered by the one - pole, low - pass filter of the AD7981 analog input circ uit made by r in and c in or by the external filter, if one is used. because the typical noise of the AD7981 is 47.3 v rms, the snr degradation due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? + = ? 2 3db 2 ) ( 2 47.3 47.3 log 20 n loss ne f snr whe re: f C 3db is the input bandwidth in mhz of the AD7981 (10 mhz) or the cutoff frequency of the input filter, if one is used. n is the noise gain of the amplifier (for example, 1 in buffer configu ration). e n is the equivalent input noise voltage of the op amp, in nv/hz. ? for ac applications, the driver must have a thd performance commensurate with the AD7981 . ? for multichannel multiplexed application s, the driver amplifier and the AD7981 analog input circuit must settle for a full - scale step onto the capacitor array at a 16 - bit level (0.00 15%, 15 ppm). in an amplifier data sheet, settling ti mes at 0.1% to 0.01% are more commonly specified , and may differ significantly from the settling time at a 16 - bit level and must be verified prior to driver selection. the ad8634 is a rail - to - rai l output, precision , low power , high temperature qualified , dual amplifier recommended for driving the input of the AD7981 . rev. 0 | page 15 of 25
AD7981 data sheet voltage reference in put the AD7981 voltage reference input, ref, has a dynamic input impedance and must therefore be driven by a low impedance source with efficient decoupling between the ref and gnd pins, as explained in the printed circuit board (pcb) layout section. whe n ref is driven by a very low impedance source , a ceramic chip capacitor is appropriate for optimum performance. the high temperature qualified low temperature drift adr225 2.5 v reference and the low power ad8634 reference buffer are recommended for the AD7981 . the ref pin must be decoupled with a cer amic chip capacitor of at least 10 f (x5r, 1206 size) for optimum performance. there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nf) between the ref and gnd pins. power supply the AD7981 uses two power supply pins: a core supply, vdd, and a digital input/output interface supply, vio. vio allows direct interface with any logic between 1.8 v and 5 v . to reduce the number of supplies needed, tie vio and vd d together. the AD7981 is independent of power supply sequencing between vio and vdd. additionally, it is insensitive to power supply variations over a wide frequency range, as shown in figure 28. 80 55 1 1000 frequency (khz) psrr (db) 10 100 75 70 65 60 12479-062 figure 28 . psrr vs. frequency the AD7981 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate , which makes the device ideal for low sampling rate (even of a few hz) and low battery - powered applications. 1 0.1 0.01 0.001 operating currents (ma) 100000 throughput rate (sps) 10000 600000 i ref 12479-055 vdd = 2.5v v ref = 5v vio = 3v i vio i vdd figure 29 . operating currents vs. throughput rate digital interface alt hou gh the AD7981 has a reduced number of pins, it offers flexibility in its serial interface modes. the AD7981 , when in cs mode, is compatible with spi, qspi ? , microwire ? , and digital hosts. the AD7981 interface can use either a 3 - wire or 4 - wire interface. a 3 - wire interface using the cnv, sck, and sdo signa ls minimizes wiring connections and is useful , for instance, in isolated applications. a 4 - wire interface using the sdi, cnv, sck, and sdo signals allows cnv, which initiates the conversions, to be independent of the readback timing (sdi). the 4 - wire inter face is useful in low jitter sampling or simultaneous sampling applications. the AD7981 , when in chain mode, provides a daisy - chain feature using the sdi input for cascading multiple adcs on a si ngle data line , similar to a shift register. the mode in which the device operates depends on the sdi level when the cnv rising edge occurs. cs mode is selected if sdi is high, and chain mode is selected if sdi is low. the sdi hold t ime is such that , when sdi and cnv are connected together, chain mode is selected. in either mode, the AD7981 offers the flexibility to optionally force a start bit in front of the data bits. thi s start bit can be used as a busy signal indicator to interrupt the digital host and to trigger the data reading. otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. the busy indicator feature is enabl ed ? in cs mode if cnv or sdi is low when the adc conversion ends (see figure 33 and figure 37 , respectively ). ? in chain mode if sck is high during the cn v rising edge (see figure 41). rev. 0 | page 16 of 25
data sheet AD7981 cs mode, 3 - wire without busy in dicator the 3 - wire cs mode without busy indicator is typically used when a single AD7981 is connected to an spi - compatible digital host. the connection diagram is shown in figure 30 , and the corresponding timing is given in fi gure 31. with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. when a conversion is initiated, it continues until completion , irrespective of the state of cnv , which can be useful, for instance, for bring ing cnv low to select other spi devices, such as analog multiplexer s . h owever, cnv must return high before the minimum conversion time elapses and then held high for the maximum conversion time to avoid the ge neration of the busy signal indicator. when the conversion is complete, the AD7981 enters the acquisition phase and p owers down. when cnv goes low, the msb is output onto sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate , provided that it has an acceptable hold time. after the 16th sck falling edge or when cnv goes high, whichever is earlier, sdo returns to high impedance . AD7981 sdo sdi data in digital host convert clk vio cnv sck 12479-015 figure 30 . 3 - wire cs mode without busy indicator connection diagram (sdi high) sdi = 1 t cnvh t conv t cyc cnv acquisition acquisition t acq t sck t sckl conversion sck sdo d15 d14 d13 d1 d0 t en t hsdo 1 2 3 14 15 16 t dsdo t dis t sckh 12479-016 fi gure 31 . 3 - wire cs mode without busy indicator serial interface timing (sdi high) rev. 0 | page 17 of 25
AD7981 data sheet cs mode , 3 - wire with busy indic ator the 3 - wire cs mode with busy indicator i s typically used when a single AD7981 is connected to an spi - compatible digital host having an interrupt input. the connection diagram is shown in figure 32 , and the corr esponding timing is given in figure 33. with sdi tied to vio, a rising edge on cnv initiates a conversion , selects cs mode, and forces sdo to high impedance. sdo is maintained in high impedance until the com pletion of the conversion , irrespective of the state of cnv. prior to the minimum conversion time, cnv can be used to select other spi devices, such as analog multiplexers, but cnv must be returned low before the minimum conversion time elapses and then he ld low for the maximum conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low. with a pull - up resistor on the sdo line, this transition can be used as an interrupt sig na l to initiate the data reading controlled by the digital host. the AD7981 then enters the acquisition phase and powers down. the data bits are clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate , provided it has an acceptable hold time. after the optional 17th sck falling edge or when cnv goes high, whichever is earlier, sdo returns to high impedance. if multiple AD7981 devices are selected at the same time, the sdo output pin handles this contention without damage or induced latch - up. it is recommended to keep this contention as short as possible to limit extra power dissipation . AD7981 sdo sdi data in irq digital host convert clk vio vio 47k cnv sck 12479-017 figure 32 . 3 - wire cs mode with busy indicator connection diagram (sdi high) t conv t cnvh t cyc acquisition acquisition t acq t sck t sckh t sckl conversion sck cnv sdi = 1 sdo d15 d14 d1 d0 t hsdo 1 2 3 15 16 17 t dsdo t dis 12479-018 figure 33 . 3 - wire cs mode with busy indicator serial interface timing (sdi high) rev. 0 | page 18 of 25
data sheet AD7981 cs mode , 4 - wire without busy in dicator the 4 - wire cs mode without busy indicator is ty pically used when multiple AD7981 devices are connected to an spi - compatible digital host. a connection diagram example using two ad798 1 devices is shown in figure 34 , and the corresponding timing is given in figure 35. with sdi high, a rising edge on cnv initiates a conversion, selects cs mode, and forces sdo to hi gh impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback (if sdi and cnv are low, sdo is driven low). prior to the minimum conversion time, sdi can be used to select other spi devices, such as analog mu ltiplexers, but sdi must be returned high before the minimum conversion time elapses and then held high for the maximum conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the AD7981 enters the acquisition phase and powers down. each adc result can be read by bringing its sdi input low, which consequently outputs the msb onto sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate , provided it has an acceptable hold time. after the 16th sck falling edge or when sdi goes high, whichever is earlier, sdo returns to high impedance , and another AD7981 can be read. digital host convert cs2 cs1 clk data in AD7981 sdo sdi cnv sck AD7981 sdo sdi cnv sck 12479-019 figure 34 . 4 - wire cs mode without busy indi cator connection diagram t conv t cyc acquisition acquisition t acq t sck t sckh t sckl conversion sck cnv t ssdicnv t hsdicnv sdo d15 d13 d14 d1 d0 d15 d14 d1 d0 t hsdo t en 1 2 3 14 15 16 17 18 30 31 32 t dsdo t dis sdi(cs1) sdi(cs2) 12479-020 figure 35 . 4 - wire cs mode without busy indicator serial interface timing rev. 0 | page 19 of 25
AD7981 data sheet cs mode , 4 - wire with busy indic ator the 4 - wire cs mode wi th busy indicator is typically used when a single AD7981 is connected to an spi - compatible digital host that has an interrupt input, and it is desired to keep cnv, which is used to sample the ana log input, independent of the signal used to select the data reading. this requirement is particularly important in applications where low jitter on cnv is desired. the connection diagram is shown in figure 36 , and the corresponding timing is given in figure 37. with sdi high, a rising edge on cnv initiates a conversion, selects cs mode, and forces sdo to high impedance. in this mode, cnv must be held hi gh during the conversion phase and the subsequent data readback (if sdi and cnv are low, sdo is driven low). prior to the minimum conversion time, sdi can be used to select other spi devices, such as analog multiplexers, but sdi must be returned low before the minimum conversion time elapses and then held low for the maximum conversion time to guarantee the generation of the busy signal indicator. when the c onversion is complete, sdo goes from high impedance to low. with a pull - up resistor on the sdo line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. the AD7981 then enters the acquisition phase and powers down. the data bits are c locked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate provided it has an acceptable hold time. after the optional 17th sck falling edge or sdi going high, whichever is earlier, the sdo returns to high impedance. AD7981 sdo sdi data in irq digital host convert cs1 clk vio 47k cnv sck 12479-021 figure 36 . 4 - wire cs mode with busy indicator connection diagram t conv t cyc acquisition t ssdicnv acquisition t acq t sck t sckh t sck l conversion sdi t hsdicnv sck cnv sdo t en d15 d14 d1 d0 t hsdo 1 2 3 15 16 17 t dsdo t dis 12479-022 figure 37 . 4 - wire cs mode with busy indicator serial interface timing rev. 0 | page 20 of 25
data sheet AD7981 chain mode without b usy indicator chain mode without busy indicator can be used to daisy - chain multiple AD7981 devices on a 3 - wire serial interface. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. data readba ck is analogous to clocking a shift register. a connection diagram example using two AD7981 devices is shown in figure 38 , and the corresponding timing is given in figure 39. when sdi and cnv are low, sdo is driven low. with sck low, a rising edge on cnv initiates a conversion, selects chain mode, and disables the b usy indicator. in this mode, cnv is held high during the conversion phase and the su bsequent data readback. when the conversion is complete, the msb is output onto sdo , and the AD7981 enters the acquisition phase and powers down. the remaining data bits stored in the internal sh ift register are clocked by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 16 n clocks are required to read back the n adcs. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate and, consequently, more AD7981 devices in the chain, provided the digital host has an acceptable hold time. the total readback time allows a reduction in the maximum conversation rate. digital host convert clk data in AD7981 sdo sdi cnv a sck AD7981 sdo sdi cnv b sck 12479-023 figure 38 . chain mode without busy indicator connection d iagram t conv t cyc t ssdisck t sckl t sck t hsdisck t acq acquisition t ssckcnv acquisition t sckh conversion sdo a = sdi b t hsckcnv sck cnv sdi a = 0 sdo b t en d a 15 d a 14 d a 13 d b 15 d b 14 d b 13 d b 1 d b 0 d a 15 d a 14 d a 0 d a 1 d a 1 d a 0 t hsdo 1 2 3 15 16 17 14 18 30 31 32 t dsdo 12479-024 figure 39 . chain mode without busy indicator serial interface timing rev. 0 | page 21 of 25
AD7981 data sheet chain mode with busy indicator chain mode with busy indicator can also be used to daisy - chain multiple AD7981 device s on a 3 - wire serial interface while providing a busy indicator. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited int erfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using three AD7981 devices is shown in figure 40, and the corresponding timing is given in figure 41. when sdi and cnv are low, sdo is driven low. with sck high, a rising edge on cnv initiates a conversion, selects chain mode, and enables the busy indicator featur e. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when all adcs in the chain have completed their conversions, the sdo pin of the adc closest to the digital host (see the AD7981 adc labeled c in figure 40 ) is driven high. this transition on sdo can be used as a busy indicator to trigger the data readback controlled by the digital host. the AD7981 then enters the acquisition phase and powers down. the data bits stored in the internal shift register are clocked out, msb first, by subsequent sck falling edges. for each adc, sdi feeds the input of the inter nal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 16 n + 1 clocks are required to read back the n adcs. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate and, consequently, more AD7981 devices in the chain, provided the digital ho st has an acceptable hold time. AD7981 c sdo sdi data in irq digital host convert clk cnv sck AD7981 b sdo sdi cnv sck AD7981 a sdo sdi cnv sck 12479-025 figure 40 . chain mode with busy indicator connection diagram t conv t cyc t ssdisck t sckh t sck t hsdisck t acq t dsdosdi t dsdosdi t dsdosdi acquisition acquisition t sckl conversion sck cnv = sdi a sdo a = sdi b sdo b = sdi c sdo c t en d a 15 d a 14 d a 13 d b 15 d b 14 d b 13 d c 15 d c 14 d c 13 d b 1 d b 0 d a 15 d a 14 d a 1 d a 0 d c 1 d c 0 d b 15 d b 14 d a 0 d a 1 d b 0 d b 1 d a 14 d a 15 d a 1 d a 0 t hsdo 1 2 3 15 16 17 4 18 19 31 32 33 34 35 47 48 49 t dsdo t dsdosdi t dsdosdi 12479-026 t ssckcnv t hsckcnv figure 41 . chain mode with busy indicator serial interface timing rev. 0 | page 22 of 25
data sheet AD7981 application s information a growing number of industries demand low power electronics that can operate reliably a t temperatures of 175 c and higher. the AD7981 enables precision analog signal processing from the sensor to the processor at high temperatures for these types of applications . figure 42 shows the simplified signal chain of the data acquisition instrument . in downhole drilling, avionics , and other extreme temperature environment applications, signals from various sensors are sampled to collect information about the su rrounding geologic formations. these sensors can take the form of electrodes, coils, piezoelectr ic, or other transducers. accelerometers and gyroscopes provide information about the inclination, vibration , and rotation ra te. some of these sensors are very low bandwidth, whereas others can have information in the aud io frequency range and higher. the AD7981 is ideal for sampling data from sensors with varying band width requirements while maintaining power efficiency and accuracy . the small footprint of the AD7981 makes it easy to include multiple channels even in space constrained layouts, such as the ver y narrow board widths prevalent in downhole tools . in addition, the flexible digital interface allows simultaneous sampling in more demanding applications, while also allowing simple daisy - chained readback for low pin count systems. for a complete selecti on of available high temperature products, see the high temperature product list and qualification data available at www.analog.com/hightemp . inst amp AD7981 adc processor power management communication to surface communications interface memory adr225 reference ad8634 ad8634 ad8634 ad8634 AD7981 adc AD7981 adc AD7981 adc ad8229 amp amp amp amp 12479-142 acoustic, temperature, resistivity, pressure sensors sensor signals inclination, vibration, rotation rate adxl206 accelerometer adxrs645 gyroscope inertial sensors figure 42 . simplified da ta acquisition system signal chain rev. 0 | page 23 of 25
AD7981 data sheet rev. 0 | page 24 of 25 printed circuit board (pcb) layout design the pcb that houses the AD7981 so that the analog and digital sections are separated and confined to certain areas of the board. the pinout of the AD7981 , with all its analog signals on the left side and all its digital signals on the right side, eases this task. avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7981 is used as a shield. fast switching signals, such as cnv or clocks, must never run near analog signal paths. avoid crossover of digital and analog signals. use at least one ground plane. it can be common or split between the digital and analog section. if the ground plane is split, join the planes underneath the AD7981 . the AD7981 voltage reference input, ref, has a dynamic input impedance and must be decoupled with minimal parasitic inductances. the reference decoupling ceramic capacitor must be placed close to, ideally right up against, the ref and gnd pins and connecting them with wide, low impedance traces. decouple the AD7981 power supplies, vdd and vio, with ceramic capacitors, typically 100 nf, placed close to the AD7981 and connected using short and wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. an example of a layout following these rules is shown in figure 43 and figure 44. 12479-028 AD7981 fig ure 43. example pcb layout of the AD7981 (top layer) 12479-027 fig ure 44. example pcb layout of the AD7981 (bottom layer)
data sheet AD7981 rev. 0 | page 25 of 25 outline dimensions compliant to jedec standards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 10 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 coplanarity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 45. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters ordering guide model 1 integral nonlinearity (inl) temperature range ordering quantity package description package option branding AD7981hrmz 2.0 lsb ?55c to +175c 50 10-lead mini small outline package [msop] rm-10 c7c 1 z = rohs compliant part. ?2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d12479-0-10/14(0)

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